High-NA EUV (0.55 NA) — Extensión del Monopolio EUV a 0.55 NA
conceptos
Definición: Próxima generación de litografía EUV con Numerical Aperture 0.55 (vs 0.33 NA actual), habilitando resolución ~8nm half-pitch sin multipatterning. En HVM inicial con Intel 18A (Panther Lake), 10 sistemas deployed en 4 customers.
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Roadmap Técnico (ASML)
| Sistema | NA | Throughput Target | Hito Clave | Timeline | |---------|-----|-------------------|------------|----------| | EXE:5000 | 0.55 | ~50-80 WPH | First shipment Intel Oregon | 2024 | | EXE:5200B | 0.55 | 135 WPH | Acceptance testing | 2026 Q2 ✓ | | EXE:5200C | 0.55 | 160 WPH | AB mode | 2027 | | EXE:5200D | 0.55 | 175 WPH | AB mode | 2028 | | EXE:5400E | 0.55 | 180+ WPH AB / 210+ AA | End of decade | 2029-2030 | | EXE:5600 (High Productivity) | 0.55 | 250+ WPH | Next generation | Post-2030 |
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HVM Milestone: Intel 18A (Julio 2026)
- Intel Foundry HVM en Intel 18A (Panther Lake, Core Ultra Series 3) usando EXE High-NA
- Capas específicas dual-qualified en High-NA + NXE (yields matched)
- Primera producción comercial High-NA en lógica
- Validación real: No slideware — producción en volumen con yields matched
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Customer Deployment (Sep 2026)
| Customer | Sistemas | Estado | |----------|----------|--------| | Intel | Multiple | HVM 18A (lead) | | SK Hynix | 1 (EXE:5200B) | M16 DRAM fab, memory development | | Customer 3 | 1-2 | Undisclosed logic | | Customer 4 | 1-2 | Undisclosed | | Total deployed | 10 sistemas | 4 customers | | Shipping/installing | 3 más | Pipeline visible |
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Throughput Economics: El desafío High-NA
| Factor | Low-NA (NXE:3800E) | High-NA (EXE:5200) | Impacto | |--------|-------------------|-------------------|---------| | NA | 0.33 | 0.55 | Resolution 1.67x better | | Field size | 26x33 mm | 26x16.5 mm (half) | Anamórfico 4x | | Throughput/WPH | 170-200 | 135→180 (roadmap) | Menor por exposición | | Sistemas por wafer equiv. | 1.0x | 1.5-2.0x | Más sistemas necesarios | | Capex por wafer/año | Baseline | 1.5-2.0x | Higher capital intensity |
Implicación: High-NA reduce multipatterning (cost/complexity) pero aumenta capex por wafer. Economics work para leading-edge logic (Intel 18A, TSMC N2, Samsung 3GAP). Memory (3D DRAM) evaluating.
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Memory Adoption: El siguiente frente
| Segmento | Estado High-NA | |----------|----------------| | Logic (Intel/TSMC/Samsung) | HVM 2026-2027 (Intel 18A, TSMC N2, Samsung 3GAP) | | DRAM (Samsung/SK Hynix/Micron) | Evaluando 3D DRAM → High-NA needed para alignment precision | | SK Hynix | EXE:5200B installed M16 (development) | | Samsung | Targeting 1nm logic ~2030 for High-NA | | Micron | Watching 3D DRAM alignment requirements |
Key insight: 3D DRAM (stacking vertical) requiere overlay precision que empuja a High-NA. Memory fabs ahora compiten por EUV allocation con logic foundries.
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Conexiones wiki
- monopolio-euv — Moat 0.33 NA consolidado, High-NA = extensión natural
- asml — Empresa, roadmap, capacity expansion
- intel — Lead customer HVM 18A
- micron-technology — EUV multiyear agreement, memory fab competition
- samsung-electronics — Logic 3GAP + DRAM 3D evaluation
- sk-hynix — EXE:5200B installed M16
- tsmc — N2 timeline, High-NA adoption
- financiacion capex ia — Capex IA $3-3.1T → EUV/High-NA demand
- ramageddon — Memory fabs compitiendo por EUV/High-NA allocation
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Gatillos de revisión
| Evento | Acción | |--------|--------| | EXE:5200C 160 WPH achieved | Validate roadmap execution | | TSMC N2 High-NA adoption confirmation | Validate logic adoption curve | | Samsung 3GAP High-NA volume | Logic adoption breadth | | SK Hynix/Micron 3D DRAM High-NA commitment | Memory adoption signal | | EXE:5200D 175 WPH / 5400E 180+ WPH | Roadmap execution validation | | Intel 18A volume ramp trajectory | Lead customer health |
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Nota de evolución 2026-09-03 (elisa-fernandez)
Concepto extraído de ASML High-NA milestones 2026. High-NA = extensión natural del moat EUV, no nuevo moat. 10 sistemas deployed, Intel 18A HVM = milestone real (no slideware). Throughput 135 WPH probado, roadmap 160→175→180+ WPH. Memory adoption = next frontier (3D DRAM). Economics: higher capex/wafer pero elimina multipatterning. Watch: Intel 18A volume ramp, TSMC N2 adoption, memory 3D DRAM commitment.